Author: Ivan Edward Sutherland
Publisher: Morgan Kaufmann
Release Date: 1999
Designers of high-speed integrated circuits face a bewildering array of choices and too often spend frustrating days tweaking gates to meet speed targets. Logical Effort: Designing Fast CMOS Circuits makes high speed design easier and more methodical, providing a simple and broadly applicable method for estimating the delay resulting from factors such as topology, capacitance, and gate sizes. The brainchild of circuit and computer graphics pioneers Ivan Sutherland and Bob Sproull, "logical effort" will change the way you approach design challenges. This book begins by equipping you with a sound understanding of the method's essential procedures and concepts-so you can start using it immediately. Later chapters explore the theory and finer points of the method and detail its specialized applications. * Explains the method and how to apply it in two practically focused chapters. * Improves circuit design intuition by teaching simple ways to discern the consequences of topology and gate size decisions. * Offers easy ways to choose the fastest circuit from among an array of potential circuit designs. * Reduces the time spent on tweaking and simulations-so you can rapidly settle on a good design. * Offers in-depth coverage of specialized areas of application for logical effort: skewed or unbalanced gates, other circuit families (including pseudo-NMOS and domino), wide structures such as decoders, and irregularly forking circuits. * Presents a complete derivation of the method-so you see how and why it works.
Author: James J. Park
Publisher: Springer Science & Business Media
Release Date: 2011-07-21
Proceedings of the International Conference on Human-centric Computing and Embedded and Multimedia Computing (HumanCom & EMC 2011) will cover topics of HumanCom and EMC, the current hot topics satisfying the world-wide ever-changing needs. Human-centric computing is to create novel solutions so that the humans are always connected, portable, and available. As with pervasive-computing, human-centric computing requires a variety of devices; however, such devices exist simply to obtain inputs from the human and are embedded in objects that humans interact with on a daily basis. Moreover, during the past couple of decades, Information Science technologies influenced and changed every aspect of our lives and our cultures. Without various Information Science technology-based applications, it would be difficult to keep information stored securely, to process information efficiently, and to communicate conveniently. Embedded computing ranges from portable devices such as digital watches and MP3 players, to large stationary installations like traffic lights, factory controllers, or the systems controlling nuclear power plants. Complexity varies from low, with a single microcontroller chip, to very high with multiple units, peripherals and networks mounted inside a large chassis or enclosure. Multimedia computing covers multimedia I/O devices, OS, storage systems, streaming media middleware, continuous media representations, media coding, media processing, etc., and also includes multimedia communications; real-time protocols, end-to-end streaming media, resource allocation, multicast protocols, and multimedia applications; databases, distributed collaboration, video conferencing, 3D virtual environments.
As advances in technology and circuit design boost operating frequencies of microprocessors, DSPs and other fast chips, new design challenges continue to emerge. One of the major performance limitations in today's chip designs is clock skew, the uncertainty in arrival times between a pair of clocks. Increasing clock frequencies are forcing many engineers to rethink their timing budgets and to use skew-tolerant circuit techniques for both domino and static circuits. While senior designers have long developed their own techniques for reducing the sequencing overhead of domino circuits, this knowledge has routinely been protected as trade secret and has rarely been shared. Skew-Tolerant Circuit Design presents a systematic way of achieving the same goal and puts it in the hands of all designers. This book clearly presents skew-tolerant techniques and shows how they address the challenges of clocking, latching, and clock skew. It provides the practicing circuit designer with a clearly detailed tutorial and an insightful summary of the most recent literature on these critical clock skew issues. Synthesizes the most recent advances in skew-tolerant design in one cohesive tutorial Provides incisive instruction and advice punctuated by humorous illustrations Includes exercises to test understanding of key concepts and solutions to selected exercises
The International Workshop on Power and Timing Modeling, Optimization, and Simulation PATMOS 2002, was the 12th in a series of international workshops 1 previously held in several places in Europe. PATMOS has over the years evolved into a well-established and outstanding series of open European events on power and timing aspects of integrated circuit design. The increased interest, espe- ally in low-power design, has added further momentum to the interest in this workshop. Despite its growth, the workshop can still be considered as a very - cused conference, featuring high-level scienti?c presentations together with open discussions in a free and easy environment. This year, the workshop has been opened to both regular papers and poster presentations. The increasing number of worldwide high-quality submissions is a measure of the global interest of the international scienti?c community in the topics covered by PATMOS. The objective of this workshop is to provide a forum to discuss and inves- gate the emerging problems in the design methodologies and CAD-tools for the new generation of IC technologies. A major emphasis of the technical program is on speed and low-power aspects with particular regard to modeling, char- terization, design, and architectures. The technical program of PATMOS 2002 included nine sessions dedicated to most important and current topics on power and timing modeling, optimization, and simulation. The three invited talks try to give a global overview of the issues in low-power and/or high-performance circuit design.
This book covers layout design and layout migration methodologies for optimizing multi-net wire structures in advanced VLSI interconnects. Scaling-dependent models for interconnect power, interconnect delay and crosstalk noise are covered in depth, and several design optimization problems are addressed, such as minimization of interconnect power under delay constraints, or design for minimal delay in wire bundles within a given routing area. A handy reference or a guide for design methodologies and layout automation techniques, this book provides a foundation for physical design challenges of interconnect in advanced integrated circuits.
Author: Egon Börger
Publisher: Springer Science & Business Media
Release Date: 2012-12-06
This state-of-the-art survey gives a systematic presentation of recent advances in the design and validation of computer architectures. The book covers a comprehensive range of architecture design and validation methods, from computer aided high-level design of VLSI circuits and systems to layout and testable design, including the modeling and synthesis of behavior and dataflow, cell-based logic optimization, machine assisted verification, and virtual machine design.
Author: Yuan Xie
Publisher: Springer Science & Business Media
Release Date: 2013-10-21
Genre: Technology & Engineering
This book explores the design implications of emerging, non-volatile memory (NVM) technologies on future computer memory hierarchy architecture designs. Since NVM technologies combine the speed of SRAM, the density of DRAM, and the non-volatility of Flash memory, they are very attractive as the basis for future universal memories. This book provides a holistic perspective on the topic, covering modeling, design, architecture and applications. The practical information included in this book will enable designers to exploit emerging memory technologies to improve significantly the performance/power/reliability of future, mainstream integrated circuits.
The 48 regular papers and 19 poster papers from the March 2000 symposium report on design techniques, processes, electronic design automation (EDA) tools, and methodologies geared toward improvement in the quality of integrated circuit designs. The regular papers are divided into sections on DSM modeling, emerging process and device technology, quality of design and EDA tools, emerging integrity issues, low power design and test, quality of IP blocks, the impact of emerging processes on design quality, quality definitions and metrics, design for manufacturability, and VDSM capacitive and inductive issues. No subject index.
This book constitutes the refereed proceedings of the 14th International Workshop on Power and Timing Optimization and Simulation, PATMOS 2004, held in Santorini, Greece in September 2004. The 85 revised papers presented together with abstracts of 6 invited presentations were carefully reviewed and selected from 152 papers submitted. The papers are organized in topical sections on buses and communication, circuits and devices, low power issues, architectures, asynchronous circuits, systems design, interconnect and physical design, security and safety, low-power processing, digital design, and modeling and simulation.